Numerical processing techniques (such as cyclical redundancy check calculations) are performed to help validate data that is digitally stored and/or transmitted. Processing systems can use a main processor (for example) to calculate a CRC calculation, but this may be unacceptable depending on the relative availability of processing throughput of the processor.
To reduce the length of time required to perform a CRC (cyclical redundancy check) calculation, dedicated CRC-engines are present in many systems on-chip (SOCs). The dedicated CRC engines typically include a CRC address generation unit and a separate read bus for accessing data directly from memory. Thus, the dedicated CRC engines are normally more complicated due to the presence of address generation unit and separate read bus, both of which complicate the bus architecture of the chip. The dedicated CRC engines typically consume substantial portions of chip area and power.